This invention relates to a raster operation device, and more particularly to a raster operation device with a fast graphic process ability for use in display units and printers using bit map memories.
Conventionally, many of character display units used for word processors and the like have adopted the code refreshing system, and these units are now required to have a graphic display ability for displaying graphs and figures. However, when the graphics-oriented bit map refreshing system is employed, it must expand dot patterns of characters in the bit map memory in display characters, resulting in a drawback of slower display process as compared with the conventional code refreshing system. This situation holds true in the case of printing the mixture of character, graphic and image data with a laser beam printer (LBP).
A method of the fast character dot pattern expansion process for a bit map memory is described, for example, in JP-A No. 60-260989 and in article entitled "256K Graphic Dual-Port Memory Incorporating Raster Operation Function and Serial Input Function", NIKKEI ELECTRONICS, pp. 243-264, published on Mar. 24, 1986 by NIKKEI McGRAW-HILL The above patent application and article propose the provision of a logical operation circuit for dealing with the raster operation on a hardware basis, in which data to be written into the bit map memory is shifted bitwise, logical operations are implemented between data in the bit map memory and writing data which has been shifted bitwise, and the result is stored in the bit map memory.
Supporting the case of reading out data from a character generator (CG) ROM which stores dot patterns of characters and writing the data into a frame buffer made of bit memory, it can be said that the word boundaries of data stored in the CG-ROM are generally inconsistent with the word boundaries of the frame buffer. On this account, in writing data into the frame buffer, the bit-shift process for aligning writing data to the word boundaries of frame buffer is required. Generally, data written in one address of the frame has a bit width smaller that the bit width of one word of the frame buffer. For example, in writing a piece of 12-bit source data which has been shifted by 7 bits into a frame buffer of 1-word (16-bit) size, the bit width of data which is actually written in an address of frame buffer is: EQU 16 bits-7 bits=9 bits
The remaining 3 bits of source data which have been left unwritten in the above writing process will undergo the writing process at the next address adjacent in the word boundary direction.
The conventional system first checks whether writing data crosses the word boundary of frame buffer and, in this case, implements on a software basis the process of writing the remaining portion of data into the next address adjacent in the word boundary direction, leaving the room of improvement from the viewpoint of fast graphic processing.